The semiconductor device industry has a market driven need to reduce IC device failures at electrical test, and to improve the operational lifetimes of IC devices. Reduced device failures may result in increased IC fabrication yield and improved device operational lifetime. Increased IC fabrication yields may result in decreased IC prices, and improved market share.
One method to reduce the number of device failures is to analyze failed devices and determine the cause of the failure. The failures may be what are known as field failures that occur at customer sites, or they may occur in products that have been sold to consumers. The failures may be found during wafer level testing at the end of wafer fabrication, or in testing after a supposedly good IC die is placed in a package, or in testing after a supposedly good IC package is placed in a printed circuit board (PCB).
It is known to examine failed devices by means of electrical testing, optical microscopes, transmitting electron microscopes (TEM), scanning electron microscopes (SEM), and other well known methods. If, for example, a particle is found that produces a short between two conductive lines in a signal layer, then action may be taken at the fabrication site to reduce particle levels, and thus increase fabrication yield. This method may be used in cases where the failure, such as the illustrative particle just discussed, is at, or near, the surface of the sample, since the failure may not be otherwise visible in an optical or an electron microscope.
However, as the semiconductor device industry has increased the level of integration of their devices and packed more capability on ever smaller semiconductor chips, the critical dimension, or size, of each transistor, each conductive line, and the spacing between lines has decreased. As a result of the smaller lines and smaller spaces, the size of a defect that may result in a device failure has also decreased, which means that the same defects and particles that were not likely to cause failures in previous generations of electronic devices are now device killers. The smaller defects are harder to detect and observe with the existing methods of detection and evaluation, and some method to enlarge the defects, which may be known as decorating, or of increasing the defect contrast as compared with the device background is needed to improve defect detection.
A method is needed to chemically etch a small area around a defect with high selectivity between the etch rates of the materials forming the defect and the materials forming the semiconductor substrate. This would improve the visual and SEM delineation, or contrast, between the defect and the substrate. In addition, or in the alternative, a layer of conductive material needs to be deposited, either selectively or non-selectively, on the surface of the substrate to decorate the defect, thus improving the ability to observe the defect. The ability to observe the defect during the localized etching and/or deposition, and the ability to stop the etching or decorating when the best image is obtained would also be beneficial. The ability to analyze the composition of the materials being etched or decorated prior to beginning the enhancement process, would improve the proper selection of the optimum etch mixture and conditions. With such an arrangement, the defect sample may be imaged during the small spot localized etching and/or deposition, and the process may continue until the desired level of decoration or enhancement structure is obtained.
These and other aspects, embodiments, advantages, and features will become apparent from the following description and the referenced drawings.